Pentium II Xeon
Pentium II Xeon logoThe first Xeon processor was released in 1998 as the Pentium II Xeon as the replacement of the Pentium Pro. The Pentium II Xeon was based on the P6 microarchitecture and used either a 440GX (a dual-processor workstation chipset) or 450NX (quad-processor, or oct with additional logic) chipset, and differed from the desktop Pentium II in that its off-die L2 cache ran at full speed. It also used a larger slot known as slot 2 Cache sizes were 512 KiB, 1 MiB and 2 MiB, and it used a 100 MT/s bus.
Pentium III Xeon
PIII XeonIn 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. The initial version (Tanner) was no different from its predecessor, save the addition of Streaming SIMD Extensions (SSE) and a few cache controller enhancements found in the Pentium III. The second version (Cascades) was somewhat more controversial, in that while it had a 133 MT/s bus it only had a 256 KiB on-die L2 cache - in other words, there was no difference between it and the desktop Pentium III, the Slot 1 versions of which were also capable of dual-processor operation. In order to remedy the situation somewhat, Intel released a second version (also called Cascades, but often suffixed to "Cascades 2 MB" to differentiate between it and the 256 KiB version) that came in two variants: with 1 MiB or 2 MiB of L2 cache. The bus speed on these models was fixed at 100 MT/s, though in practice the cache was able to offset this.
Xeon & Xeon MP (32-bit)
The Xeon (dropping "Pentium" from the name) was introduced in mid-2001. The initial variant that used the new NetBurst architecture, Foster, was slightly different from the desktop Pentium 4. It served as a decent workstation chip, but it was almost always outperformed in server applications by the older Cascade 2 MiB core and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive.
At most two Foster processors could be accommodated in an SMP system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MiB L3 cache. This improved performance slightly, but not by enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions.
In 2002 a 130 nm version of the Xeon (this time codenamed Prestonia) was released, now supporting Intel's new Hyper-Threading technology and having a 512 KiB L2 cache. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM) was released to support this processor in servers, and shortly afterwards the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). The new Xeon performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
The Xeon MP version of the Prestonia was the Gallatin, which had an L3 cache of 1 MiB or 2 MiB. This version also performed much better than Foster MP, and was popular in servers. Later on, Intel's experience with the 130 nm process allowed them to port the Xeon over to the Gallatin core and also allowed a Xeon MP with 4 MiB cache.
Xeon & Xeon MP (64-bit)
Due to a severe lack of success with Intel's Itanium and Itanium 2 processors, the 90 nm version of the Pentium 4 (Prescott) was built with support for 64-bit instructions (called EM64T by Intel, though it was much the same as AMD's AMD64 instruction set), and a Xeon version codenamed Nocona was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. Generally speaking the Xeon was noticeably slower than AMD's Opteron, though it could also be much faster in situations where Hyper-Threading came into play.
A slightly updated core called Irwindale was released in early 2005, differing from Nocona in having twice the L2 cache and the ability to reduce its clockspeeds in situations that didn't need much processing power. However, performance numbers generated through independent tests (available here) which have been conducted show the Irwindale is still outperformed by the AMD Opteron processor.
64-bit Xeon MPs were introduced in April 2005. The cheaper version was Cranford, an MP version of Nocona. The more expensive version was Potomac; a Cranford with 8 MiB of L3 cache.
DP-capable, 90 nm "Paxville DP"
Intel released the first Dual-Core Xeon, codenamed Paxville DP, on 10 October 2005. Paxville DP is a dual-core version of the NetBurst Irwindale, with 4 MiB of L2 Cache (2 MiB per core). The one Paxville DP model that has been released runs at 2.8 GHz and features an 800 MT/s front side bus.
7000-series "Paxville MP"
An MP-capable version of Paxville DP, codenamed Paxville MP, was released on 1 November 2005. There are two versions: one with 2 MiB of L2 Cache (1 MiB per core), and one with 4 MiB of L2 (2 MiB per core). Paxville MP is called the Dual-Core Xeon 7000-series. Paxville MP ranges between 2.67 and 3.0 GHz (model numbers 7020-7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.
LV, Core Duo-based "Sossaman"
On 14 March 2006, Intel released the processor codenamed Sossaman as the Dual-Core Xeon LV (Low Voltage). Sossaman is a low-power, ultradense environment, dual-processor capable chip based on the Core Duo processor technology. As such, it supports the same feature set as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing but with 32-bit support only.
On 23 May 2006, Intel released the Dual-Core Xeon codenamed Dempsey. Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst processor built on a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.67 and 3.73 GHz (model numbers 5030-5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MiB of L2 Cache (2 MiB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: Socket J, also known as LGA 771.
On 26 June 2006, Intel released the Dual-Core Xeon codenamed Woodcrest; it was the first Intel Core microarchitecture processor to be launched on the market. It is a server and workstation version of the Intel Core 2 processor. Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.
It has a 1333 MT/s FSB in most models, except for the 5110 and 5120, which have a 1066 MT/s FSB, with the fastest processor clocking in at 3.0 GHz. All Woodcrests use LGA 771 and all but the 5160 and 5148LV have a TDP of 65 W, which is much less than the previous generation of 130 W. The 5160 has a TDP of 80 W, still much less than 130 W, and the 5148LV, which will be available in Q3 2006, has a TDP of 40 W. All models support EM64T, the XD bit, and Virtualization Technology, with Demand-Based Switching only on Dual-Core Xeon 5140 or above.
Released on August 29, 2006 , the 7100 series, codenamed Tulsa, is an improved version of Paxville MP, built on a 65 nm process, with 2 MiB of L2 cache (1 MiB per core) and up to 16 MiB of L3 cache. It uses Socket 604 . Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 to 3.33 GHz (model numbers 7110N-7140N), and the M-line ranges from 2.6 to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MiB to 16 MiB across the models. 
Intel released rebadged versions of the desktop Core 2 Duo (Conroe) as the Dual-Core Xeon 3000-series at the end of September 2006. Model numbers are 3040, 3050, 3060, and 3070; other than the name, they are otherwise identical to Core 2 Duo models E6300, E6400, E6600, and E6700 . Unlike all previous Xeon-badged processors, they only support single-CPU operation.
A quad-core successor of Woodcrest for DP segment, consisting of two Woodcrest dies on a multi-chip module, with 8 MiB of L2 cache (4 MiB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released Clovertown at November 14, 2006  with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 to 2.66 GHz (the Xeon E5335, however, will not be available until Q1'2007). The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB . All but the X5355 have a TDP of 80 W. The X5355 has a TDP of 120 W. A low-voltage version of Clovertown with a TDP of 50 W has a model number L5310 .
This article contains information about a scheduled or expected future product.
It may contain unverified or unreliable information, and may not reflect the final version of the product.
Intel will release rebadged versions of its upcoming quad-core Core 2 Quad processor as the Xeon 3200-series in early 2007. The models will be the X3210 and X3220, running at 2.13 and 2.4 GHz, respectively . Like the 3000-series, these models will only support single-CPU operation.
A quad-core processor, partially based on Woodcrest, using the new Common System Interface (CSI) bus, which will be shared with the Itanium 2 processors of its generation (beginning with the "Tukwila" core). Whitefield would have had 16 MiB of L2 cache. and manufactured using the 65 nm process initially, and the 45 nm process later, but it was cancelled from the processor roadmap, and replaced with another processor, codenamed Tigerton. Whitefield was the first full processor being worked on at Whitefield, Bangalore, and hence the name.
A quad-core, MP-capable processor to be released in place of Whitefield  .
A successor to Tigerton .
A 45 nm successor to Tigerton, which may be either a quad-core or an octa-core processor  . Dunnington was originally based on Whitefield, but with Whitefield cancelled, Dunnington's details are less clear .
Harpertown is said to be a 45 nm, eight-core processor with 12 MiB of L2 cache . An older rumour stated that it was simply the 45 nm shrink of Woodcrest , but that has since changed.
Quad-core processor based on Intel's upcoming Nehalem microarchitecture .
Nehalem-based MP-capable processor (the correct spelling may be either Beckton or Becton).